1. Technical Field
The present invention relates to chip dicing methods, and more particularly, to a chip dicing method that yields chip less susceptible to cracking.
2. Related Art
In fabricating semiconductor chips, in order to reduce interconnect RC (Resistance-Capacitance) delays, reduce crosstalk between adjacent metal lines, and reduce power consumption of the chips, low-K (K is dielectric constant) materials are used as dielectric materials instead of traditional dielectric materials such as silicon dioxide. However, low-K materials are generally more brittle and less adhesive than traditional dielectric materials. This aggravates the cracking problem during the packaging step. The cracking problem happens when different layers of a chip separate, especially at the chip's corners, due to thermal expansion mismatch of materials of the different layers of the chip. This cracking problem is more likely to occur during the packaging step because this step usually involves subjecting the chip to different temperatures in order to thermally cure some materials in the chip. It has been determined that this cracking problem usually happens at corners of the chip where stress is greatest compared with the remaining region of the chip.
Therefore, there is a need for a structure of a novel semiconductor chip that is less susceptible to cracking than that of prior art. Also, there is a need for a method for fabricating the novel semiconductor chip.